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Blindsided by a glitch
The blindside blitz. The quarterback’s greatest fear. The big hit that arrives with no warning and the cover bypassed. In SoC design, particularly in clock domain crossing (CDC) analysis, RTL designers...
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Vivado, inside the new Xilinx design suite
The Vivado Design Suite has been released by Xilinx after four years of development and a year of beta testing. It is a highly integrated design environment with a completely new generation of...
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Eliminating iterations in gigahertz ASIC handoff
Working at advanced geometries brings timing closure challenges that make it difficult for design teams to complete their projects on schedule. For better predictability and to avoid time-consuming...
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Hardware description languages such as SystemVerilog use the symbol ‘X’ to describe any unknown logic value. If a simulator is unable to decide whether a logic value should be a ‘1’, ‘0’, or ‘Z’ for...
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Dynamic power optimization
FinFETs present a number of problems with respect to dynamic power consumption. Part of the issue is that dynamic power rises in importance because the three-walled devices exhibit reduced leakage from...
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